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1 features ? 15ns maximum access time ? asynchronous operation, functionally compatible with industry-standard 128k x 32 srams ? cmos compatible inputs and output levels, three-state bidirectional data bus - i/o voltage 3.3 volts, 1.8 volt core ? operational environment: - total-dose: 300 krad(si) - sel immune: >100 mev-cm 2 /mg - let th (0.25): 53.0 mev-cm 2 /mg - memory cell saturated cross section: 1.67e-7cm 2 /bit - neutron fluence: 3.0e14n/cm 2 - dose rate - upset 1.0e9 rad(si)/sec - latchup >1.0e11 rad(si)/sec ? packaging options: - 68-lead ceramic quad flatpack (6.19 grams) ? standard microcircuit drawing 5962-03236 - qml q & v compliant part introduction the ut8r128k32 is a high-p erformance cmos static ram organized as 131,072 words by 32 bits. easy memory expansion is provided by active low and high chip enables (e1 , e2), an active low output enable (g ), and three-state drivers. this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to the device is accomplish ed by taking chip enable one (e1 ) input low, chip enable two (e2) high and write enable (w ) input low. data on the 32 i/o pins (dq0 through dq31) is then written into the locati on specified on the address pins (a0 through a16). r eading from the devi ce is accomplished by taking chip enable one (e1 ) and output enable (g ) low while forcing write enable (w ) and chip enable two (e2) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the 32 input/output pins (dq0 through dq31) are placed in a high impedance state when the device is deselected (e1 high or e2 low), the outputs are disabled (g high), or during a write operation (e1 low, e2 high and w low). figure 1. ut8r128k32 sram block diagram memory array 256k x 16 pre-charge circuit column select row select a1 a2 a4 a5 a6 a7 a8 a9 data control i/o circuit data control a10 a11 a12 a13a14 a15 dq(15) to dq(0) dq(31) to dq(16) e1 hhwe w e2 lhwe ? ? ? ? ? ? g a0 a16 low word read circuit high word read circuit a3 standard products ut8r128k32 128k x 32 sram data sheet march 2009 www.aeroflex.com/memories
2 pin names device operation the ut8r128k32 has six control inputs called chip enable 1 (e1 ), chip enable 2 (e2), write enable (w ), half-word enables (hhwe /lhwe ) and output enable (g ); 17 address inputs, a(16:0); and 32 bidirectional data lines, dq(15:0). e1 and e2 chip enables control device selection, active, or standby modes. asserting e1 and e2 enables the device, causes i dd to rise to its active value, and decodes the 17 address inputs to select one of 131,072 words in the memory. w controls read and write operations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. a(16:0) address w write enable dq(31:0) data input/output g output enable e1 chip enable 1 (active low) v dd1 power (1.8v) e2 chip enable 2 (active high) v dd2 power (3.3v) hhwe lwhe high half-word enable low half-word enable v ss ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 top view dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 v ss dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 v ss a0 a1 a2 a3 a4 a5 hhwe v ss lhwe w a6 a7 a8 a9 a10 v dd1 v dd1 a11 a12 a13 a14 a15 a16 e1 g e2 v dd2 v ss nc nc nc v dd2 v ss dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 figure 2. 15ns sram pinout (68) 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 g w e2 e1 lhwe hhwe i/o mode mode x x x h x x dq(31:16) 3-state dq(15:0) 3-state standby x x l x x x dq(31:16) 3-state dq(15:0) 3-state standby l h h l l h dq(31:16) 3-state dq(15:0) data out low half-word read l h h l h l dq(31:16) data out dq(15:0) 3-state high half-word read l h h l l l dq(31:16) data out dq(15:0) data out word read x l h l l l dq(31:16) data in dq(15:0) data in word write x l h l l h dq(31:16) 3-state dq(15:0) data in low half-word write x l h l h l dq(31:16) data in dq(15:0) 3-state high half-word write h h h l x x dq(31:16) dq(15:0) all 3-state 3-state x x h l h h dq(31:16) dq(15:0) all 3-state 3-state
3 read cycle a combination of w and e2 greater than v ih (min) and e1 less than v il (max) defines a read cycle. read access time is measured from the latt er of chip enable, output enable, or valid address to valid data output. sram read cycle 1, the address access in figure 3a, is initiated by a change in address inputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(31:0) after the specified t av q v is satisfied. outputs remain active throughout the entire cycle. as long as chip enables and output enable are active, the address inputs may change at a rate equal to th e minimum read cycle time (t avav ). sram read cycle 2, the chip enable-controlled access in figure 3b, is initiated by the latter of e1 and e2 going active while g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the 32-bit word addressed by a(16:0) is accessed and appears at th e data outputs dq(31:0). sram read cycle 3, the output enable-controlled access in figure 3c, is initiated by g going active while e1 and e2 are asserted, w is deasserted, and the ad dresses are stable. read access time is t glqv unless t av q v or t etqv have not been satisfied. write cycle a combination of w and e1 less than v il (max) and e2 greater than v ih (min) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the ou tputs are placed in the high- impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enab le-controlled access in figure 4a, is defined by a write terminated by w going high, with e1 and e2 still active. the write pulse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by e1 or e2. unless the outputs have been previously placed in the high-impedance state by g , the user must wait user must wait t wlqz before applying data to the 32 bidirectional pins dq(31:0) to avoid bus contention. write cycle 2, the chip enable -controlled access in figure 4b, is defined by a write terminated by either of e1 or e2 going inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by either e1 or e2 going active. for the w initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the sixteen bidirectional pins dq(31:0) to avoid bus contention. word enables separate half-word enable controls (lhwe and hhwe ) allow individual 16-bit word accesses. lhwe controls the lower bits dq(15:0). hhwe controls the upper bits dq(31:16). writing to the device is performed by asserting e1 , e2 and the half- word enables. reading the devi ce is performed by asserting e1 , e2, g , and the half-word enables while w is held inactive (high). operational environment the ut8r128k32 sram incorporates special design, layout, and process features which a llows operation in a limited environment. table 2. operational enviro nment design specifications 1 notes: 1. the sram is immune to la tchup to particles >100mev-cm 2 /mg. 2. 90% worst case particle environment, geosynchronous orbit, 100 mils of aluminum. supply sequencing no supply voltage sequencing is required between v dd1 and v dd2 . hhwe lhwe operation 0 0 32-bit read or write cycle 0 1 16-bit high half-word read or write cycle (low half-word bi-direction pins dq(15:0) are in 3 -state) 1 0 16-bit low half-word read or write cycle (high half-w ord bi-direction pins dq(31:16) are in 3 -state) 1 1 high and low half-word bi- directional pins remain in 3-state, write function disabled total dose 300k rad(si) heavy ion error rate 2 8.9x10 -10 errors/bit-day
4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limit s indicated in the operationa l sections of this specific ation is not recommended. exposure to absolu te maximum rating conditions for extended periods may af fect device reliability and performance. 2. test per mil-std-883, method 1012. recommended operating conditions notes: 1. for increased noise im munity, supply voltage (v dd1 ) can be increased to 2.0v. if not tested, all applicable dc and ac characteristics are guranteed by characterization at vdd1 (max) = 2.0v. symbol parameter limits v dd1 dc supply voltage -0.3 to 2.1v v dd2 dc supply voltage -0.3 to 3.8v v i/o voltage on any pin -0.3 to 3.8v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.2w t j maximum junction temperature +150 c jc thermal resistance, junction-to-case 2 5 c/w i i dc input current 5 ma symbol parameter limits v dd1 positive supply voltage 1.7 to 1.9v 1 v dd2 positive supply voltage 3.0 to 3.6v t c case temperature range (p) screening: 25 c (c) screening: -55 to +125 c (w) screening: -40 to +125 c v in dc input voltage 0v to v dd2
5 dc electrical charac teristics (pre and post-radiation)* unless otherwise noted, tc is per the temperature ordered symbol parameter condition min max unit v ih high-level input voltage .7*v dd2 v v il low-level input voltage .3*v dd2 v v ol low-level output voltage i ol = 8ma,v dd2 =v dd2 (min) .2*v dd2 v v oh high-level output voltage i oh = -4ma,v dd2 =v dd2 (min) .8*v dd2 v c in 1 input capacitance ? = 1mhz @ 0v 12 pf c io 1 bidirectional i/o capacitance ? = 1mhz @ 0v 12 pf i in input leakage current v in = v dd2 and v ss -2 2 a i oz three-state output leakage current v o = v dd2 and v ss v dd2 = v dd2 (max), g = v dd2 (max) -2 2 a i os 2, 3 short-circuit output current v dd2 = v dd2 (max), v o = v dd2 v dd2 = v dd2 (max), v o = v ss -100 +100 ma i dd1 (op 1 )v dd1 supply current operating @ 1mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v , i out = 0 v dd2 = v dd2 (max) v dd1 = 1.9v 15 ma v dd1 = 2.0v 18 ma i dd1 (op 2 )v dd1 supply current operating @ 66mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd2 = v dd2 (max) v dd1 = 1.9v 85 ma v dd1 = 2.0v 105 ma i dd2 (op 1 )v dd2 supply current operating @ 1mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v , i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 1ma i dd2 (op 2 )v dd2 supply current operating @ 66mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 12 ma
6 notes: * for devices procured with a total ionizing dose tolerance guar antee, the post-irrad iation performance is guaranteed at 25c p er mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. measured only for initial qua lification and after process or design changes that could affect input/output capacitance. 2. supplied as a design limit but not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. 4. v ih = v dd2 (max), v il = 0v. i dd1 (sb) 4 supply current standby @ 0hz cmos inputs , i out = 0 e1 = v dd2 -0.2, e2 = gnd v dd2 = v dd2 (max) v dd1 = 1.9v 11 ma v dd1 = 2.0v 18 ma i dd2 (sb) 4 v dd1 = v dd1 (max) 100 a i dd1 (sb) 4 supply current standby a(16:0) @ 66mhz cmos inputs , i out = 0 e1 = v dd2 - 0.2, e2 = gnd, v dd2 = v dd2 (max) v dd1 = 1.9v 11 ma v dd1 = 2.0v 18 ma i dd2 (sb) 4 v dd1 = v dd1 (max) 100 a
7 ac characteristics read cycle (pre and post-radiation)* v dd1 = v dd1 (min), v dd2 = v dd2 (min); unless otherwise noted, tc is per the temperature ordered notes: * for devices procured with a total ionizi ng dose tolerance guarantee, the post-irrad iation performance is guaranteed at 25c p er mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. guaranteed but not tested. 2. three-state is defined as a 200mv change from steady-state output voltage. 3. the et (chip enable true) notation refers to the latter falling edge of e1 or rising edge of e2. 4. the ef (chip enable false) notation refers to the latter rising edge of e1 or falling edge of e2. symbol parameter 8r128k32-15 min max unit t avav 1 read cycle time 15 ns t av q v address to data valid 15 ns t axqx 2 output hold time from address change 3 ns t glqx 2,1 g -controlled output enable time 0 ns t glqv g -controlled output data valid 7 ns t ghqz 2 g -controlled output three-state time 7 ns t etqx 2,3 e-controlled output enable time 5 ns t etqv 3 e-controlled access time 15 ns t efqz 2,4 e-controlled output three-state time 2 7ns t blqx 1 lhwe , hhwe enable to output in low-z 0 ns t bhqz lhwe , hhwe enable to output in high-z 7 ns t blqv lhwe , hhwe enable to data valid 10 ns
8 assumptions: 1. e1 and g < v il (max) and e2 and w > v ih (min) a(16:0) dq(31:0) figure 3a. sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data assumptions: 1. g , hhwe , lhwe < v il (max) and w > v ih (min) a(16:0) figure 3b. sram read cycle 2: chip enable access latter of e1 low and e2 high data valid t efqz t etqv t etqx dq(31:0) figure 3c. sram read cycl e 3: output enable access a(16:0) dq(31:0) g t ghqz assumptions: 1. e1 < v il (max) , e2 and w > v ih (min) t glqv t glqx t avqv data valid lhwe /hhwe t blqx t bhqz t blqv
9 ac characteristics write cycle (pre and post-radiation)* v dd1 = v dd1 (min), v dd2 = v dd2 (min); unless otherwise noted, tc is per the temperature ordered notes: * for devices procured with a total ionizi ng dose tolerance guarantee, the post-irrad iation performance is guaranteed at 25c p er mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. tested with g high. 2. three-state is defined as 200mv cha nge from steady-state output voltage. symbol parameter 8r128k32-15 min max unit t avav 1 write cycle time 15 ns t etwh chip enable to end of write 12 ns t av e t address setup time for write (e1 /e2- controlled) 0 ns t av w l address setup time for write (w - controlled) 1 ns t wlwh write pulse width 12 ns t whax address hold time for write (w - controlled) 2 ns t efax address hold time for chip enable (e1 /e2- controlled) 2 ns t wlqz 2 w - controlled three-state time 5 ns t whqx 2 w - controlled output enable time 4 ns t etef chip enable pulse width (e1/ e2 - controlled) 12 ns t dvwh data setup time 7 ns t whdx data hold time 2 ns t wlef chip enable controlled write pulse width 12 ns t dvef data setup time 7 ns t efdx data hold time 2 ns t av w h address valid to end of write 12 ns t whwl 1 write disable time 3 ns t blwh lhwe , hhwe low to write high 12 ns t blef lhwe , hhwe low to enable high 12 ns
10 assumptions: 1. g < v il (max). (if g > v ih (min) then q(31:0) will be in three-state for the entire cycle.) w t avwl figure 4a. sram write cycle 1: w - controlled access a(16:0) q(31:0) e1 t avav d(31:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz t avwh t whwl e2 lhwe / hhwe t blwh
11 t efdx assumptions & notes: 1. g < v il (max). (if g > v ih (min) then q(31:0) will be in three-state for th e entire cycle.) 2. either e1 / e2 scenario can occur. a(16:0) figure 4b. sram write cycle 2: enable -chip controlled access w e1 d(31:0) applied data e1 q(31:0) t wlqz t etef t wlef t dvef t avav t avet t avet t blef t efax t efax or e2 e2 lhwe / hhwe
12 data retention characteristics (pre and post-radiation) * (v dd2 = v dd2 (min), 1 sec dr pulse) symbol parameter temp minimum maximum unit v dr v dd1 for data retention -- 1.0 -- v i ddr 1 data retention current -40 c -55 c 25 c 125 c -- -- -- -- 600 600 600 12 a a a ma t efr 1,2 chip deselect to data retention time -- 0 -- ns t r 1,2 operation recovery time -- t avav -- ns v dd1 data retention mode t r 1.7v v dr > 1.0v figure 5. low v dd data retention waveform t efr e1 v dd2 v in <0.3v dd2 cmos e2 v ss v in >0.7v dd2 cmos 1.7v 90% input pulses 10% < 2ns < 2ns cmos 0.0v v dd2 -0.05v v dd2 dut zo = 50-ohms v dd2 c l = 50pf r term 100-ohms test point r term 100-ohms notes: 1. measurement of data output occurs at the lo w to high or high to lo w transition mid-point (i.e., cmos input = v dd2 /2). figure 6. ac test load and input waveforms notes: * for devices procured with a total ionizing dose tolerance guarantee, the post-irradia tion performance is guaranteed at 25c p er mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. e1 = v dd2 or e2 = v ss all other inputs = v dd2 or v ss 2. v dd2 = 0 volts to v dd2 (max)
13 packaging notes: 1. all exposed metallized areas are gold plated over nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in acc ordance with mil-prf-38535. figure 7. 68-lead ceramic quad flatpack
14 ordering information 128k x 32 sram ut **** ** - * * * * * lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) screening: (c) = hirel temperature range flow (-55 c to +125 c) (p) = prototype flow (w) = extended industrial temperature range flow (-40 c to +125 c) package type: (w) = 68-lead ceramic quad flatpack access time: (15) = 15ns access time (68 cqfp) device type: (8r128k32) =128k x 32 sram notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when or dering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex colorado spri ngs manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. hirel temperature range flow per aeroflex colorado spring s manufacturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed. 5. extended industrial range flow per aeroflex colorado spri ngs manufacturing flows document . devices are tested at -40 c, room temp, and 125 c. radiation neither tested nor guaranteed.
15 128k x 32 sram: smd 5962 - ******* ** lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (x) = 68-lead ceramic quad flatpack class designator: (q) = qml class q (v) = qml class v device type (01) = 15ns access time, cmos i/o, 68-lead ceramic quad flatpack (-55 c to +125 c) (02) = 15ns access time, cmos i/o, 68-lead ceramic quad flatpack (-40 c to +125 c) drawing number: 03236 total dose: (r) = 100k rad(si) (f) = 300k rad(si) federal stock class designator: no options ** * notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
16 notes
17 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex utmc microelectronic systems inc. (aeroflex) reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a product or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado spring s - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel

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